The present invention relates to integrated circuits incorporating trench structures and to methods for fabricating such integrated circuits.
Fabrication of trenches--i.e. grooves etched in the substrate of an integrated circuit which (regardless of their length) have an aspect ratio (depth to width ratio) greater than 2.5:1, or a width less than 3 microns and a depth greater than one micron--is desirable in several areas of VLSI processing, but this fabrication step presents several distinctive difficulties, at which the present invention is aimed.
Current VLSI trends in CMOS and bipolar technologies require the development of nonencroachment isolation techniques to improve utilization of silicon area for active device fabrication while effectively reducing latch-up susceptibility. That is, when LOCOS isolation is used to separate moat (active device) regions, the field oxide will grow laterally to encroach on the moat regions at the same time it is grown to its desired thickness. This is also a problem with other isolation technologies: the separation required between nearest-neighbor active devices across the isolation structure is likely to be many times the minimum geometry. The need for compact isolation is particularly critical to CMOS VLSI efforts, since present doping levels limit N-to-P tank spacing to 4 to 6 microns. To reduce the required n+ to p+ spacing, silicon trench dry etch processing may be employed to generate deep yet narrow silicon wells between cells that are subsequently refilled with CVD oxide or polysilicon to effect device isolation while maintaining high density and still avoiding latchup.
Another area where trench processing is a critical need is in DRAMs (dynamic random access memories). Higher packing densities may be achieved for dynamic MOS memories if the cell area consumed by the planar storage capacitor can be decreased without decreasing the capacitance below soft error levels. This can be achieved by placing the capacitor dielectric on the sidewalls of a silicon trench etched sufficiently deep to have the equivalent surface area of the planar capacitor. Note that trenches in such applications, unlike those required for isolation, do not tend to be long trenches.
However, the characteristics of the silicon trench must be very carefully controlled to achieve satisfactory results in such applications. The trench cross-sectional profile is of particular concern; for instance, trench profiles where the silicon is undercut with respect to the patterning mask or where "grooving" is exhibited near the bottom of the trench are commonly observed with conventional trench etch processing. Even minutely undercut sidewall profiles will readily promote void formation during the subsequent CVD refill operations commonly used in both trench isolation and trench capacitor processing. These voids are a problem because they can act as a contaminant depository. Moreover, a later etchback step may reopen the void, producing huge filament problems if a conductor is sought to be patterned thereafter. Moreover, etchback to achieve a truly planar surface within the trench, as is desirable for some advanced processes, becomes impossible. The trench bottom "grooving" can also be exceedingly deleterious: it can degrade the dielectric integrity of a trench capacitor and can promote high, stress-related Si defect densities during thick thermal oxidation.
"Grooving" is believed to be due to nonuniformity generated at the beginning of the etch process. That is, near the beginning of the etch process, the edges of the trench will be exposed to bombardment both by ions coming straight in and by ions which have been slightly deflected by the sidewalls of the trench or by the hard mask, so that the trench will be etched slightly deeper at its edges than near its center. This nonuniformity can be carried forward to the later stages of etching, by the complex effects of autosputtering, so that a trench etched using prior art methods is very likely to have grooves in its bottom next to its sidewalls.
Thus it is an object of the present invention to provide a silicon trench etch which will provide a trench without grooves or spikes or other undesirable topography on the floor of the trench.
A further problem of the prior art is a peculiar form of undercut which may be referred to as retrograde undercut, or bowing. This is different from the ordinary forms of undercut in that the amount of undercut will be almost zero next to the mask, and will typically increase with depth for a distance of a micron or so. This retrograde undercut is believed to be due to scattering of ions from the mask material at the opposite edge of the trench.
Thus it is an object of the present invention to provide a silicon trench etch which will provide a trench with straight (unbowed) sidewalls, and without grooves or other undesirable topography on the floor of the trench.
In the prior art, the natural way to achieve control of trench profile would be to make the etch conditions slightly less anisotropic, e.g. by increasing pressure. However, this approach does not work, for several reasons: first, more isotropic etches make the eventual width of the trench less controllable. Second, if the trench sidewall is anywhere near vertical (as is necessary to retain the advantages which motivate use of a trench in the first place), merely using a more isotropic etch will still tend to produce undercut near the top of the trench, so that voids occur during refill. If the anisotropicity is reduced enough that voids do not occur, the "trench" structure will be so wide that the compact spacing which is much of the object of using trenches will be lost.
The present invention solves these and other problems of the prior art by providing a silicon trench etch process that takes advantage of a selective sidewall deposition to eliminate "grooving" and to provide trenches having controllably and reproducibly sloped trench sidewalls which are positively sloped at a steep angle. The trenches thus provided by the present invention are conductive to subsequent successful refill processing, without sacrificing linewidth control. The process used in the present invention exhibits oxide sidewall deposition that takes place in a slow, continuous, and uniform fashion during the silicon trench etching step. (This is thought to be achieved because portions of the mask are forward sputtered during the etch process, and portions of the forward sputtered mask material (possibly in combination with silicon etch products) produce a thin deposited non-stoichiometric oxide on the sidewalls of the trench as etching proceeds.) In this manner, the deeper portions of the silicon etch are defined on the pattern edge by the sidewall oxide, generating sloped silicon sidewalls as the deposition builds up. In addition, the sidewall deposition prevents "grooving" at the trench bottom. This is probably attributable to a shadowing by the deposition of the trench bottom edge and/or a difference in the ion deflection coefficient off of oxide versus silicon.
In the prior art, there has been experimentation with chemistries which slowly deposit silicon oxide while etching silicon trenches to achieve much higher "selectivity" to the mask SiO.sub.2. See Horwitz, Reactive Sputter Etching of Silicon with Very Low Mask-material Etch Rates, 28 IEEE TRANSACTIONS ON ELECTRON DEVICES 1320, which is hereby incorporated by reference. However, this prior art attempt led to uncontrolled deposition: since the deposited oxide is sourced from the gas flow, its deposition locations are determined by the gas flow, and are not (as in the present invention) conveniently and reliably located with respect to the etching process. In the reported prior art, the sidewall oxide deposition had negative consequences in terms of the wall profile, promoting some degree of effective undercut of the mask.
A particular advantage of the processing innovations taught by the present invention is that they produce trenches having a straight, sloped sidewall, without grooving at the bottom or undercut at the top, wherein the slope of the sidewall is steep but controllable. The processing parameters which are controlled to vary the trench sidewall slope are the DC self-bias voltage of the silicon etch step, and the introduction of a small amount of a species such as BCl.sub.3 which tends to produce oxide etching. That is, sidewall oxide deposition will be completely eliminated if 3-5 sccm of BCl.sub.3 is introduced into the silicon etch mixture, and introduction of lesser amounts of BCl.sub.3 will reduce sidewall oxide deposition and therefore steepen the sidewall angle of the trench being etched. Thus, the present invention provides a reproducible process for fabricating trenches having a controlled sidewall slope at a predetermined angle between 80 and 89 degrees, and a flat trench bottom. Moreover, these trenches can easily made to depths formerly impractical, e.g. 8 microns or more.
This structure is itself novel, since there has heretofore been no way to make such an ideal trench. The availability of precisely controlled steep sidewall slope is highly advantageous, since it means that refill problems can be avoided, and also because implanting steps can (if desired) reach the sidewalls of the trench. This may be particularly desirable in trench isolation applications, where such an implant can be used to remove the leakage path due to turn-on of the parasitic transistor at the face of the trench sidewall. It may also be useful in trench capacitor applications, where such an implant can serve as a "Hi-C" implant, or may serve other purposes. (In this case, the hard mask could be made of a composite material, such as oxide/nitride/oxide or poly/oxide, so that some of the hard mask would be left to keep the trench mask pattern for implanting after the throat-choking oxide is removed.)
In particular, the present invention permits fabrication of trench capacitors using very deep trenches. A key problem of trench capacitors generally is getting the capacitance of a minimum geometry capacitor high enough. The present invention contributes to solving two aspects of this problem: first, the deeper a trench the greater its capacitance will be (for a given specific capacitance on the sidewalls). Second, the present invention permits fabrication of trench capacitors so deep that they can reach right through the lightly doped epitaxial layer where active devices are formed, into the heavily doped substrate. Where the substrate is so heavily doped, it is particularly critical to avoid cusping at the bottom of the trench: any geometrically caused electric field increase in more likely to cause breakdown here than in more lightly doped regions, for two reasons: first, since the depletion width is narrower, the electric field across the depletion layer will be higher. Second, the presence of heavy doping here may mean that the quality of a grown oxide is not quite equal to that grown on more lightly doped silicon. Third, the stress present around the cusping will mean that the grown oxide will have less thickness in this critical area than elsewhere. For example, one embodiment of the present invention provides a DRAM cell using 8 micron deep trenches, and deeper trenches could easily be built also.
Thus, the present invention provides at least the following advantages, in addition to others mentioned in this application:
1. A very deep trench can be reproducibly etched with excellent control of geometries.
2. The present invention provides a trench in silicon which has straight (unbowed) sidewalls, and which does not have grooves or other undesirable topography on the floor of the trench.
3. The trenches provided by the present invention are conducive to subsequent successful refill processing, without sacrificing linewidth control.
4. The present invention provides trenches having controllably and reproducibly sloped trench sidewalls which are positively sloped at a steep angle.
5. The present invention (in certain embodiments thereof) provides a DRAM cell having a capacitor in a trench 6 microns or more deep, so that relatively high capacitance can be attained in a trench cell.
6. The present invention (in certain embodiments thereof) provides a DRAM cell having a capacitor in a trench which extends down into a heavily-doped substrate (below the epitaxial layer in which active devices are built), so that relatively high capacitance can be attained in a trench cell.
7. The present invention (in certain embodiments thereof) provides a DRAM cell having a vertical transistor overlying a storage capacitor in a trench 6 microns or more deep, so that relatively high capacitance can be attained in a trench cell while maintaining good pass transistor performance and good trench refill characteristics.
According to the present invention there is provided: A process for etching trenches in silicon, comprising the steps of: providing a patterned hard mask over a silicon substrate; plasma etching exposed portions of said silicon substrate under etch conditions such that the material of said hard mask is forward sputtered to induce deposition on sidewalls of said trench during etching.
According to the present invention there is provided: A process for etching trenches in silicon, comprising the steps of: providing a silicon substrate having thereon a patterned hard mask comprising silicon oxides and being defined to expose said silicon only in predetermined trench locations; etching a trench in said predetermined trench locations of said silicon substrate under conditions such that oxides of silicon are continually deposited on sidewalls of said trench during etching, wherein substantially all of the atomic oxygen in said oxides on said trench sidewalls derives from said hard mask.
According to the present invention there is provided: An integrated circuit incorporating trench capacitors, comprising: a dynamic random access memory comprising an array of memery cells, said cells in said array individually comprising a pass transistor in series with a storage capacitor, at least one plate of said storage capacitor being formed in silicon at the face of a trench; wherein said trench has straight sidewalls without bowing or undercut at a positive sidewall angle in the range of 80 to 89 degrees.
According to the present invention there is provided: An integrated circuit including trench isolation, comprising: a silicon substrate including therein a plurality of active device areas comprising transistors; a plurality of trenches separating said active device areas in a predetermined isolation pattern; wherein each said trench has straight sidewalls without bowing or undercut at a positive sidewall angle in the range of 80 to 89 degrees.